1. Technical Field
The present invention relates to conductive substructures of a multilayered laminate and associated methods of fabrication.
2. Related Art
FIGS. 1, 2, and 3 illustrate conductive substructures that may appear in a conventional multilayered laminate. FIG. 1 illustrates a 0S2P substructure 10, FIG. 2 illustrates a 2S0P substructure 20, and FIG. 3 illustrates a 1S1P substructure 30. Definitionally, the substructures in this application are described by an adjective of the form nSmP, wherein n and m are non-negative integers, wherein S stands for xe2x80x9csignal plane,xe2x80x9d and wherein P stands for xe2x80x9cpower plane.xe2x80x9d Thus, xe2x80x9c0S2Pxe2x80x9d connotes 0 signal planes and 2 power planes (n=0, m=2), xe2x80x9c2S0Pxe2x80x9d connotes 2 signal planes and 0 power planes (n=2, m=0), and xe2x80x9c1S1Pxe2x80x9d connotes 1 signal plane and 1 power plane (n=1, m=1). A conventional multilayered laminate comprises stacked substructures which may include any or all of the 0S2P, 2S0P, and 1SLP substructures.
A power plane is characterized by its inclusion of a continuously conductive layer. For example, the 0S2P substructure 10 in FIG. 1 comprises a power plane 11 which includes a continuously conductive layer 12, and a power plane 13 which includes a continuously conductive layer 14. As another example, the 1S1P substructure 30 in FIG. 3 comprises a power plane 31 which includes a continuously conductive layer 32. Although not shown in FIGS. 1 and 3, a power plane may include one or more holes within the continuous conductive layer. The continuous conductive layer of a power plane may include copper.
A signal plane is characterized by its inclusion of a layer comprising conductive circuitry. For example, the 2S0P substructure 20 in FIG. 2 comprises a signal plane 21 which includes a conductive circuitry 22, and a signal plane 23 which includes a conductive circuitry 24. As another example, the 1S1P substructure 30 in FIG. 3 comprises a signal plane 33 which includes a conductive circuitry 34. The conductive circuitry of a signal plane may include copper.
A substructure may include a via through its thickness, such as a conductively plated via 27 in the 2S0P substructure 20 in FIG. 2.
In a substructure, a power plane cannot conductively contact another power plane, a power plane cannot conductively contact a signal plane, and a signal plane cannot conductively contact another signal plane. Thus, power planes and signal planes may be insulatively separated by a dielectric layer. As a first example, the 0S2P substructure 10 in FIG. 1 comprises a dielectric layer 15 that insulatively separates the power plane 11 from the power plane 13. As a second example, the 2S0P substructure 20 in FIG. 2 comprises a dielectric layer 25 that insulatively separates the signal plane 21 from the signal plane 23. As a third example, the 1S1P substructure 30 in FIG. 3 comprises a dielectric layer 35 that insulatively separates the power plane 31 from the signal plane 33.
Unfortunately, some or all of the preceding 0S2P, 2S0P, and 1S1P substructures prevent improved wiring density within the substructures, and thus within the overall multilayered laminate that includes the 0S2P, 2S0P, and 1S1P substructures. With the 2S0P substructure of FIG. 2, for example, the conductive circuitry 22 may be required to be oriented at about right angles to the conductive circuitry 24 in order to minimize cross-talk (i.e., noise) due to electromagnetic radiative coupling between the conductive circuitry 22 and the conductive circuitry 24; i.e., if x and y axes represent orthogonal directions within the signal planes 21 and 23, then the conductive circuitry 22 would be oriented in the x direction if the conductive circuitry 24 were oriented in the y direction, and vice versa. The aforementioned directional constraints on the conductive circuitry 22 and the conductive circuitry 24 translates into a constraint on wireability (i.e., a constraint on how high the wiring density can be within the signal planes 21 and 23).
Additionally, with less than optimum wiring density, the geometrical size of the overall multilayered laminate will have to be large enough to accommodate all of the wiring that is physically required for the intended application. The increased size is undesirable, because of at least two reasons. A first reason is that space is likely to be at a premium and a conservation of space is generally strived for in the electronic packaging industry. A second reason is that an increased size is more expensive because of increased material requirements and, more importantly, a requirement to drill longer through holes through the substructures and the overall multilayered laminate.
Moreover, if a highly pliable or flexible dielectric material is used in the substructures, then all three of the 0S2P, 2S0P, and 1S1P substructures will be required to have a thickness that is large enough for the substructures to have sufficient structural rigidity. Note that an organic dielectric material for use in a chip carrier may exemplify a highly pliable or flexible dielectric.
There is a need for conductive substructures for use in multilayered laminates such as chip carriers, wherein the conductive substructures improve wireability, reduce substructure and overall laminate thicknesses, and result in lower fabrication costs.
The present invention provides a method for forming a 0S1P substructure, comprising:
providing a sheet of conductive material with an exposed first surface and an exposed second surface;
forming a hole through the sheet of conductive material; and
applying a layer of dielectric material to the exposed first surface after the step of forming a hole.
The present invention provides a method for forming a 0S3P substructure, comprising
providing a sheet of conductive material having an exposed first surface and an exposed second surface;
forming a hole through the sheet of conductive material;
applying a first layer of dielectric material to the first surface of the sheet of conductive material, after the step of forming a hole;
applying a second layer of dielectric material to the second surface of the sheet of conductive material, after the step of forming a hole;
applying a first layer of conductive material on the first layer of dielectric material; and
applying a second layer of conductive material on the second layer of dielectric material.
The present invention provides a method for forming a 2S1P substructure, comprising:
providing a sheet of conductive material having an exposed first surface and an exposed second surface;
forming a hole through the sheet of conductive material;
applying a first layer of dielectric material to the first surface of the sheet of conductive material, after the step of forming a hole;
forming a first signal plane on the first layer of dielectric material;
applying a second layer of dielectric material to the second surface of the sheet of conductive material, after the step of forming a hole; and
forming a second signal plane on the second layer of dielectric material.
The present invention provides an electrical structure, comprising: a multilayered laminate that includes a plurality of substructures, wherein a dielectric material of a dielectric layer insulatively separates each pair of successive substructures, and wherein a subset of the plurality of substructures is selected from the group consisting of a 0S1P substructure and a 0S3P substructure, the 0S1P substructure and a 2S1P substructure, the 0S3P substructure and the 2S1P substructure, the 0S1P substructure and the 0S3P substructure and the 2S1P substructure, and the 0S3P substructure.
The present invention provides a 0S3P substructure, comprising:
a sheet of conductive material having a hole therethrough;
a first layer of dielectric material on a first surface of the sheet of conductive material;
a second layer of dielectric material on a second surface of the sheet of conductive material;
a first layer of conductive material on the first layer of dielectric material, said first layer of conductive material having a hole therethrough; and
a second layer of conductive material on the second layer of dielectric material, said second layer of conductive material having a hole therethrough.
The present invention has the advantages of improving wireability, reducing substructure and overall laminate thicknesses, and resulting in lower fabrication costs. In particular, the power plane of the 2S1P substructure of the present invention serves as a shielding layer that eliminates the cross-talk that may occur with the 2S0P substructure of the related art. Thus the power plane of the 2S1P substructure improves wireability and conserves space. Additionally, the interior power plane of the 0S1P, 0S3P, 2S1P substructures of the present invention provides added structural rigidity that makes it possible to reduce the thickness of these substructures, especially if these substructures include a highly pliable or flexible dielectric material such as may characterize an organic dielectric material.